Digital Design Engineer

Job Summary

Seeking a digital design engineer with experience and interest in developing complex mixed-signal ICs for frequency control, clock generation, network synchronization, and other timing applications. Candidate will be involved in all aspects of the design process from system conceptualization to mass production. The candidate will participate in digital system architecture, block- and system-level RTL design/coding, algorithm development, digital circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), firmware development (some ICs include embedded processors), digital design verification, and full-chip mixed-signal verification.  Responsibilities include detailed documentation, and test vector development, lab test and evaluation, and other activities as required for the achievement of high-volume production.

Responsibilities

• • Digital design specification, design, analysis, and HDL (Verilog/System Verilog) coding
  • Behavioral modeling of analog and mixed signal circuits
  • Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc.
  • Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development
  • Validation of silicon functionality, behavior, and performance

Minimum Requirements

• • Digital design specification, design, analysis, and HDL (Verilog/System Verilog) coding
  • Behavioral modeling of analog and mixed signal circuits
  • Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc.
  • Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development
  • Validation of silicon functionality, behavior, and performance

Additional Skills (one or more of these are highly desirable)

• • Digital design specification, design, analysis, and HDL (Verilog/System Verilog) coding
  • Behavioral modeling of analog and mixed-signal circuits
  • Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc.
  • Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development
  • Validation of silicon functionality, behavior, and performance

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