Sr. Manager, IC Design Engineering

Job Description

Skyworks Irvine, our Corporate Headquarters is home to industry leading R&D and Product Development teams in the beautiful beach and university adjacent city of Irvine, California. Irvine and the surrounding areas of Orange County offer an active and vibrant, multi-cultural lifestyle for new grads or established families alike, with the best public schools and one of the safest neighborhoods in the country. With the legendary Southern California weather and a modern growing city around us, Skyworks Irvine is in one of the most desirable locations. 
 
When you join the team in Irvine you will become a part of our uniquely collaborative, multi-disciplinary and open Engineering Community and work in tandem with all the other engineering and support teams. From day 1, your success is our priority, and you’ll be working with other team members to help support you as you become an integral part of our broad and diverse team. Come join our highly successful and rapidly growing team of RF engineers and develop industry-leading products while advancing your career at the same time!
 
We are looking for a highly motivated IC Design Engineering Manager to contribute to RF Front End designs. You will work with other analog/RFIC and module designers for creating most advanced architectures and designs of IC. As an RFIC Engineering Manager you will be responsible for the analysis, design, simulation and development of RF LNA and SW IPs for next generation mobile devices using SOI, SiGe and other technologies. The candidate will be expected to innovate and work in a fast-paced market to help to define and realize products as a chip lead.

Required Qualifications

• BS Degree with 15+ years or MS + 12 years or PhD + 8 years of RF/Analog IC related experience using SOI, SiGe, CMOS
• Proven leadership in RF/Analog product design innovation.
• Strong experience in RF frontend Switch/PA/LNA design and product developments.
• Strong understanding of analog control and bias circuits such as POR, bias, bandgap, LDO, OPamp, charge pump, fuse etc.
• Experienced in implementing on-chip ESD protection strategies for HBM/CDM on IC
• Demonstrated experience debugging, resolving and applying techniques to mitigate RF/Analog design issues and optimum layout for performance, and die size trade off.
• Proficient with Cadence tools
• Layout experience using the Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on RF/Analog layouts

Preferred Qualifications

• Good understanding of MIPI standard and decoder design
• Good communication and presentation skills
• Demonstrated project management and talent management skills. Strong leadership skills with the ability to engage and motivate engineering talent, define and set deliverables, plan resources, manage schedule, drive design methodology improvement, and achieve desired results. 

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