Sr. Manager, Engineering

Job Description

The Process Engineering group at Skyworks in Woburn, Massachusetts is responsible for developing and supporting all wafer fabrication processes used to produce Skyworks’ diverse portfolio of products.  The primary device technologies include HBT, GaN, BiFET, pHEMT and BiHEMT at various performance nodes.  The group works closely with the Advanced Technology Development team to develop technologies and with the Manufacturing Operations team to deliver world-class quality products to market.

Responsibilities

• Fill the role of lead engineer and manager for a group of process engineers/technicians in the Lithography area, which is responsible for all photolithographic processes as well as metrology.
• Support daily production to ensure on-time-delivery of top quality product.  Occasionally requires leading a team to rapidly contain yield/quality excursions and drive corrective actions.
• Support Advanced Technology Development projects to achieve site and corporate objectives.
• Lead the group to pursue continuous improvement opportunities affecting key metrics.  Includes applying solutions systemically to leverage improvements for maximum benefit.
• Participate in staffing planning/decisions to ensure long-term site and corporate objectives.
• Support professional development of the individuals in the group to stay in tune with industry trends, extend the state of the art and enhance the group’s technical depth and breadth.
• Build teamwork and cohesiveness within the group, and champion collaboration between engineering groups to improve the wellbeing and performance of the overall organization.
• Work with Operations synergistically, following a “work cell” model, to optimize the overall performance of the Lithography area and enhance the skills/knowledge of Operations personnel.

Qualifications

• At a minimum, a BS in engineering, physics, chemistry, material science or related discipline, plus at least 10 years of experience in micro-electronics process engineering with primary experience in photolithography.  Additional “must haves” include:
  • Expert knowledge of i-line photolithography and how it’s applied in compound semiconductor wafer fabrication processes.
  • Extensive experience with ASML 5500 steppers, TEL ACT-8 and Mark-5 coat/develop tracks, and linked systems.
  • Extensive experience with high viscosity polymers such as polyimides and PBO.
  • A thorough understanding of 1X contact/close-proximity photolithography.
  • In depth knowledge of metrology as it relates to photolithography (e.g. CDs, overlay, particles and film thicknesses).
  • Experience with CAD software (e.g. Cadence) to perform new product design reviews.
  • Experience specifying, configuring, qualifying and supporting photolithographic equipment (e.g. coat/develop tracks, steppers, ovens and metrology tools) for high volume production.
  • Strong leadership qualities, proven capable of directing and mentoring engineering staff to achieve technology transfer/development objectives between non-copy-exactly wafer fabs.

Additional Qualifications

• Metrics driven, data directed, detail oriented and very strong in core engineering principles.
• An insatiable desire to understand cause and effect, and the mechanisms that connect them. 
• Expert level knowledge and practical experience applying structured problem-solving methods, SPC, DOE, MSA and ANOVA to identify and control or eliminate root causes of variation.
• Expert level data analysis skills using tools such as JMP and Exensio/Spotfire.
• History of successfully leading teams to 1) continuously improve process control and 2) rapidly contain yield/quality excursions, identify root causes and implement effective corrective actions.
• Ability to work effectively with engineering peer groups to influence change and drive improvements in a dynamic and collaborative environment that values lasting results.
• Initiative to address and appropriately escalate problems to achieve rapid resolution.
• Excellent verbal and written “360 degree” communication skills.
• Ability and willingness to work in a cleanroom semiconductor processing environment.
• Ability to work with other engineering resources across various shifts.
• An ideal candidate will have at least a basic understanding of common PCM test structures and parameters.
• An ideal candidate will also have a basic knowledge of Lean and the Theory of Constraints.

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